1. Field of the Invention
The present invention relates to flip-flops, and more particularly, to a D flip-flop.
2. Background of the Related Art
D flip-flops are a type of registers used in many semiconductor circuits. D flip-flops can be classified into rising edge D flip-flops where a data output is produced at a rising edge of a clock signal and falling edge D flip-flops where the data output is produced at a falling edge of the clock signal.
Input/output operations of a D flip-flop are accomplished during a cycle of the clock signal. In particular, during one half cycle of the clock signal, data is input and there is no output, and during the other half cycle of the clock signal, data is output and there is no input. FIG. 1 depicts symbols for a prior art D flip-flop circuit.
FIG. 2 depicts elements of the related art D flip-flop shown in FIG. 1. The D flip-flop of FIG. 1 has two latches such as a master latch and a slave latch. The master latch receives a clock signal CLK and a data signal D and produces an interior output signal Q'. The slave latch receives the output signal Q' of the master latch, stored in the master latch at a rising edge of the clock signal CLK, and produces an output signal Q having a logical value equal to that of the data D and a complementary signal /Q.
A detailed description of the master latch and the slave latch will now be provided. The data signal D is transmitted to an inverter 2 through a transmission gate 1. An output signal of the inverter 2 is the output signal Q' of the master latch. The output signal Q' is fed back into an input stage of the inverter 2 through an inverter 5 and a transmission gate 4. Thus, the inverter 2 has two input paths respectively controlled by the transmission gates 1 and 4. The transmission gate 1 controls a direct input path of the data signal D and the transmission gate 4 controls a feedback path. The two transmission gates 1 and 4 are controlled by the clock signal CLK. When the clock signal CLK is low level, the transmission gate 1 is turned on, and when the clock signal CLK is high level, the transmission gate 4 is turned on.
On/off operations of the two transmission gates 1 and 4, which are alternatively turned on (or alternatively turned off), determine a data output mode and a data hold mode of the master latch. If the transmission gate 1 is turned on, the output Q' is produced and the feedback path is not established. If the transmission gate 4 is turned on, the two inverters 2 and 5 and transmission gate 4 form a closed loop to continuously maintain the logical value of the output signal Q'.
The slave latch includes transmission gate 6, which receives the output signal Q' of the master latch, and the inverter 7 connected in series. An output signal of the inverter 7 is the output signal Q of the slave latch. The output signal Q is fed back into an input stage of the inverter 7 through an inverter 9 and a transmission gate 8. Thus, the inverter 7 has two input paths each respectively controlled by the two transmission gates 6 and 8. The transmission gate 6 controls a direct input path of the output signal Q', and the transmission gate 8 controls a feedback path. The two transmission gates 6 and 8 are controlled by the clock signal CLK. The transmission gate 6 is turned on when the clock signal CLK is high level and the transmission gate 8 is turned on when the clock signal CLK is low level.
On/off operations of the two transmission gates 6 and 8, which are alternatively turned on (or alternatively turned off), determines a data output mode and a data hold mode of the slave latch. When the transmission gate 6 is turned on, the inverter 7 produces the output signal Q and the feedback path is not established. When the transmission gate 8 is turned on, the two inverters 7 and 9 and the transmission gate 8 form a closed loop and the logical value of the output signal Q is continuously maintained. At this time, the output signal from the other inverter 9 is an inverted signal /Q of the output signal Q.
Accordingly, the data output operation and the data hold operation in the master latch and the slave latch are complementary. When the clock signal CLK goes to a low level, the transmission gate 1 of the master latch is turned on to input a data signal D to the master latch. But the transmission gate 6 of the slave latch 6 is turned off so that the newly input data signal D is not output. When the clock signal CLK goes to a high level, the transmission gate 1 of the master latch is turned off so that a new data signal D is not input to the master latch, but the logical value of the previously input data signal D is maintained. The transmission gate 6 of the slave latch is turned on to provide an inverted signal of the output signal Q' of the master latch (i.e., an inverted signal of the previously input data signal D) through the inverter 7 of the slave latch. Thus, an output signal Q having the same logical value of the input data D is produced by the slave latch.
As described above, the related art at D flip-flop has various disadvantages. To constitute the related art D flip-flop, a number of the transmission gates and inverters are required. The D flip-flop shown in FIG. 2 includes five inverters and four transmission gates. Implementing a number of logical gates with MOS transistors can increase an interior capacitance such as parasitic capacitance. An increase of the interior capacitance increases power consumption, and decreases an operating speed because of the number of elements.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.